1. Field of the Invention
The present invention relates generally to analog-to-digital (ADC) converters, and in particular, to a method, apparatus, and article of manufacture for an ADC with a voltage ramp that has both a linear and non-linear portion. Furthermore, this ADC can be precisely calibrated to provide a linear output.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by reference numbers enclosed in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
Single-slope column-parallel Analog-to-Digital Converters (ADCs) are very popular for CMOS (complementary metal-oxide-semiconductor) imagers. However such ADCs have limited resolution for a given speed, or equivalently, low speed for a given resolution. For example, 256 clock cycles are required to achieve 8 bit resolution. Accordingly, what is needed is an ADC that provides high resolution and high speed.